A processor does not finish one instruction before starting the next. Follow the stream as instructions overlap through five stages, one advancing on every tick of the clock.
A processor has to run a long list of instructions. Doing them strictly one after another wastes most of the chip most of the time, because each step of an instruction uses only a small part of the hardware.
A pipeline solves this by splitting instruction handling into stages and letting different instructions occupy different stages at once. It works like an assembly line: while one instruction is being executed, the next is being decoded and the one after that is being fetched.
Because each stage then only has to do one small job, so it can be made short and fast. Once all stages are full, a finished instruction rolls off the end on every clock cycle instead of once every five cycles â the same units, simply kept busy on different instructions.
The gain is not free: keeping stages in step needs careful handling, because instructions sometimes depend on each other. Those moments are where stalls and hazards come from.
A stream of instructions waits to be run. Normally they would be handled one at a time, each finishing fully before the next begins. The pipeline changes that.
The fetch stage reads the next instruction from memory. As soon as it hands it on, fetch immediately turns to the one after it.
Decode looks at the instruction and determines what operation it is, which registers it needs and where its result should go. Meanwhile fetch is already loading the next one.
The execute stage does the arithmetic or logic the instruction calls for, using operands read from the register file. This is the stage that actually produces a value.
If the instruction needs to touch memory, this stage reads or writes it. Instructions that only work on registers simply pass through.
Finally the result is written back into the register file, completing the instruction. Because the stages overlap, by now several later instructions are already partway through the pipeline.
It is a way of splitting instruction work into stages so that different instructions occupy different stages at the same time. Instead of finishing one instruction before starting the next, the CPU overlaps them.
A common set is fetch, decode, execute, memory and write-back. Fetch gets the instruction, decode works out what it means, execute performs the operation, memory loads or stores data, and write-back saves the result.
Each stage does one small job, so it can be short and quick. Once all stages are full, an instruction finishes every clock cycle instead of every five â the same parts, simply kept busy on different instructions.
A stall is a pause in the flow. It happens when the next instruction cannot proceed â for example because it needs a result that is not ready yet or must wait on memory. Stalls reduce the ideal overlap.
A hazard is a situation where overlapping instructions interfere, such as one instruction needing data another is still computing. Processors handle hazards by stalling, forwarding results early, or reordering instructions.
No. More stages can raise the clock rate, but each one adds overhead, and mispredicted branches cost more to unwind. Real designs balance depth against these penalties.